FIG. 1 is a circuit diagram showing a conventional semiconductor integrated circuit (IC) device including a power-on reset circuit. In this figure, the conventional IC device includes a power supply potential node 1 supplied with a power supply potential V.sub.DD, and a ground potential node 2 connected to the ground potential. The conventional IC device further includes a power-on reset circuit 20 which receives power supply potential V.sub.DD, and generates a power-on reset signal. When the power supply potential rises from the ground potential to a prescribed potential V.sub.DD (for example, 5 V), the power-on reset signal is maintained at LO for a prescribed time period, and then is changed to HI.
The conventional IC device further includes an internal circuit 10 having, for example, sequential logic circuits or memory devices which are driven by power supply potential V.sub.DD. When the power-on reset signal is applied to internal circuit 10, the latter is immediately reset to desired logic states.
Referring again to FIG. 1, power-on reset circuit 20 includes a capacitor 3 connected between ground potential node 2 and a connection node 5, a resistor 4 connected between power supply potential node 1 and connection node 5, and a buffer 22 connected between connection node 5 and a reset terminal of internal circuit 10.
When power supply potential V.sub.DD is applied, a voltage V.sub.-- RC at connection node 5 of time delay circuit 21 rises from zero up to high level V.sub.DD, but with a delay in accordance with the time constant RC of resistance R and capacitance C, of the resistor and the capacitor. The delayed voltage V.sub.-- RC is provided to buffer 22, which has a threshold voltage V.sub.thresh. The buffer outputs a power-on reset signal of low level when V.sub.-- RC is smaller than V.sub.thresh, and of high level when V.sub.-- RC is higher V.sub.thresh.
Referring to the timing chart of FIG. 2, the conventional IC device operates as follows. At the time of power-up, power supply potential V.sub.DD starts rising from the ground potential at time t0, and reaches the prescribed potential at time t1. At this time, power-on reset signal is LO, and voltage V.sub.-- RC starts rising toward V.sub.DD with a time-constant. The time profile of voltage V.sub.-- RC can be obtained by the following equation: ##EQU1##
Voltage V.sub.-- RC will reach the threshold voltage value V.sub.thresh after a delay time t.sub.d, which is also known as interval of power-on reset time. Neglecting a delay time of the buffer itself, the value of t.sub.d is found by the following equation: ##EQU2##
When the threshold value is reached, power-on reset signal PWR.sub.-- ON.sub.-- RESET is changed from LO to HI. The power-on reset signal is applied to sequential logics or memory devices of internal circuit 10, to reset them to desired logic states. After this time, the power-on reset signal is maintained at high level and thereby the sequential logics or the memory devices are not influenced by the power-on reset signal.
As described immediately above, the power-on reset signal can be obtained using the RC time delay of circuit 21. For a longer delay, a capacitance of capacitor 3 must be increased. Since capacitors having a large capacitance occupy a larger space on a device chip, such capacitors should be formed outside the device chip, as in FIG. 1. This reduces the degree of integration of the device chip, and inevitably requires allocating an input/output pin of the device chip should be for the external capacitor.